1. Field of the Invention
This invention relates to the field of dielectric layers formed on substrates within microelectronics fabrications. More particularly, the invention relates to silicon containing glass dielectric layers employed with composite layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications comprise microelectronics active devices fabricated upon substrates interconnected by patterned microelectronics conductor layers separated by microelectronics dielectric layers. As device dimensions have diminished and device switching speeds have increased, circuit operation has become increasingly limited by capacitance delays due to close proximity of conductor lines. Efforts to minimize capacitance have been devoted to improving the quality of the dielectric materials forming the layers separating the conductor interconnection pattern.
While silicon containing materials such as, for example, silicon oxide and silicon nitride have been satisfactory as dielectric materials from forming inter-metal dielectric (IMD) layers these materials are not without disadvantages for this purpose. The dielectric constants of these materials, whose values range from 4 to 8, result in undesirably high capacitance leading to increased signal coupling and cross-talk between adjacent conductor lines. Dielectric materials with lower dielectric constants which are suitable for forming dielectric layers have been developed such as silsesquioxane spin-on-glass (SOG) dielectric materials, amorphous carbon dielectric materials and organic polymer spin-on-polymer (SOP) dielectric materials. Such materials are readily formed as dielectric layers, and have advantages when formed as composite dielectric layers upon silicon containing dielectric underlayers which have been previously formed upon a microelectronics fabrication substrate.
In particular, spin-on dielectric materials having dielectric constants ranging from 2 to 3 have found application as low dielectric constant dielectric materials for inter-level metal dielectric (IMD) layers. Organic polymer spin-on-polymer (SOP) dielectric materials and silsesquioxane spin-on-glass (SOG) dielectric materials deposited upon silicon oxide underlayers may be employed to form inter-level metal dielectric (IMD) layers within microelectronics fabrications. However, the formation of low dielectric constant composite dielectric layers employing spin-on-glass (SOG) dielectric materials such as hydrogen silsesquioxane (HSQ) formed upon silicon oxide underlayers is not without problems.
For example, the formation of via contact holes through inter-level metal dielectric (IMD) layers employing photolithographic masking and etching methods may result in absorption or trapping of materials of the via contact hole formation processes, particularly moisture. This may result in subsequent contamination of the microelectronics fabrication, and is commonly referred to as the "via poisoning" problem. The contaminated or "poisoned" via problem may be exacerbated if the silicon oxide underlayer is porous and retains material, particularly moisture, from the etching of the organic polymer low dielectric constant dielectric upper layer of the IMD layer. This is commonly observed when the silicon oxide underlayer is formed employing the method of sub-atmospheric pressure thermal chemical vapor deposition (SACVD) or near atmospheric pressure chemical vapor deposition (APCVD) in order to obtain a planar surface. Surface planarity is characteristically more readily achieved by these methods, but the silicon oxide layers are less dense than silicon oxide layers produced by, for example. plasma enhanced chemical vapor deposition (PECVD) or thermal oxidation of silicon.
It is therefore towards the goal of forming upon a substrate employed within a microelectronics fabrication an inter-level metal dielectric (IMD) layer with attenuated "poisoned via" contamination and inter-level capacitance that the present invention is generally directed.
Various methods have been disclosed for forming inter-level metal dielectric (IMD) layers upon substrates within microelectronics Fabrications.
For example. Jain, in U.S. Pat. Ser. No. 5,621,241, discloses a method for forming a dielectric stack layer with improved planarity and uniformity upon a semiconductor device with both high and low aspect ratio conductor lines on a common level. The method employs high density plasma chemical vapor deposition of silicon dioxide over conductors followed by a plasma enhanced chemical vapor deposition of a silicon dioxide layer which serves as a polish layer.
Further, Wang et al., in U.S. Pat. No. 5,679,606, disclose a method for forming a planar inter-metal dielectric (IMD) dielectric layer over closely spaced metal lines on a semiconductor surface. The method employs electron cyclotron resonance (ECR) method for forming a silicon oxide layer, followed by formation of a gap filling dielectric layer employing simultaneous deposition/sputtering to smooth out the surface of the IMD layer. The sequence is repeated as desired to build up the thickness of the resulting IMD layer.
Finally, Lou, in U.S. Pat. No. 5,759,906, discloses a method for forming an inter-level metal dielectric (IMD) layer suitable for multi-level interconnections. The method employs plasma enhanced chemical vapor deposition (PECVD) to form a silicon dioxide layer followed by a mutiple layer of at least four spin-on-glass (SOG) or spin-on-polymer (SOP) dielectric layers, each layer baked to minimize via poisoning problems. The multiple stack of dielectric layers is covered with a capping layer of undoped or doped silicon containing glass layers formed by plasma enhanced chemical vapor deposition (PECVD), providing a layer for chemical mechanical polish planarization without disturbing the SOG or SOP layers.
Desirable in the art of microelectronics fabrications are additional methods for forming inter-level metal dielectric (IMD) layers upon substrates employed within microelectronics fabrications. More particularly desirable in the art of integrated circuit microelectronics fabrications are additional methods for forming low dielectric constant dielectric layers upon underlying dielectric layers upon substrates employed within integrated circuit microelectronics fabrications to form inter-level metal dielectric (IMD) layers wherein formation of via contact holes is accompanied by attenuated via poisoning.
It is towards these goals that the present invention is generally and more specifically directed.